Techniques for random maskin in hardware

Jovan Dj.  Golic

Paper 2005/026

Techniques for random maskin in hardware

Jovan Dj. Golic

Abstract

A new technique for Boolean random masking of the logic AND operation in terms of NAND logic gates is presented and its potential for masking arbitrary cryptographic functions is pointed out. The new technique is much more efficient than a previously known technique, recently applied to AES. It is also applied for masking the integer addition. In addition, new techniques for the conversions from Boolean to arithmetic random masking and vice versa are developed. They are hardware oriented and do not require additional random bits. Unlike the previous, software-oriented techniques showing a substantial difference in the complexity of the two conversions, they have a comparable complexity being about the same as that of one integer addition only. All the techniques proposed are in theory secure against the first-order differential power analysis on the logic gate level. They can be applied in hardware implementations of various cryptographic functions, including AES, (keyed) SHA-1, IDEA, and RC6.

Metadata

Available format(s): PS
Category: Implementation
Publication info: Published elsewhere. Unknown where it was published
Keywords: power analysis random masking logic circuits
Contact author(s): golic @ inwind it
History: 2005-02-04: received
Short URL: https://ia.cr/2005/026
License: CC BY

BibTeX

@misc{cryptoeprint:2005/026,
      author = {Jovan Dj.  Golic},
      title = {Techniques for random maskin in hardware},
      howpublished = {Cryptology ePrint Archive, Paper 2005/026},
      year = {2005},
      note = {\url{https://eprint.iacr.org/2005/026}},
      url = {https://eprint.iacr.org/2005/026}
}