Synthesis of Secure FPGA Implementations

Kris Tiri; Ingrid Verbauwhede

Paper 2004/068

Synthesis of Secure FPGA Implementations

Kris Tiri and Ingrid Verbauwhede

Abstract

This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure digital design flow. Compared with an existing technique to implement Dynamic Differential Logic on FPGA, the technique saves a factor 2 in slice utilization. Experimental results also indicate that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase in slice utilization when compared with a normal non-secure single ended implementation.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Unknown where it was published
Keywords: differential power analysis FPGA synthese
Contact author(s): tiri @ ee ucla edu
History: 2004-02-29: received
Short URL: https://ia.cr/2004/068
License: CC BY

BibTeX

@misc{cryptoeprint:2004/068,
      author = {Kris Tiri and Ingrid Verbauwhede},
      title = {Synthesis of Secure {FPGA} Implementations},
      howpublished = {Cryptology {ePrint} Archive, Paper 2004/068},
      year = {2004},
      url = {https://eprint.iacr.org/2004/068}
}