Paper 2021/1212

SPEEDY on Cortex--M3: Efficient Software Implementation of SPEEDY on ARM Cortex--M3

Hyunjun Kim and Kyungbae Jang and Gyeongju Song and Minjoo Sim and Siwoo Eum and Hyunji Kim and Hyeokdong Kwon and Wai-Kong Lee and Hwajeong Seo

Abstract

The SPEEDY block cipher suite announced at CHES 2021 shows excellent hardware performance. However, SPEEDY was not designed to be efficient in software implementations. SPEEDY's 6-bit sbox and bit permutation operations generally do not work efficiently in software. We implemented SPEEDY block cipher by applying the implementation technique of bit slicing. As an implementation technique of bit slicing, SPEEDY can be operated in software very efficiently and can be applied in microcontroller. By calculating the round key in advance, the performance on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e. cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. Through this, we conclude that SPEEDY can show good performance on embedded environments.