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Paper 2021/004

LLMonPro: Low-Latency Montgomery Modular Multiplication Suitable for Verifiable Delay Functions

Ismail San

Abstract

This study presents a method to perform low-latency modular multiplication operation based on both Montgomery and Ozturk methods. The design space exploration of the proposed method on a latest FPGA device is also given. Through series of experiments on the FPGA using an high-level synthesis tool, optimal parameter selection of the proposed method for the low-latency constraint is also presented for the proposed technique.

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Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Keywords
Montgomery modular multiplicationlow-latency implementationhigh-level synthesisFPGA.
Contact author(s)
isan83 @ gmail com
History
2021-02-16: revised
2021-01-02: received
See all versions
Short URL
https://ia.cr/2021/004
License
Creative Commons Attribution
CC BY
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