Cryptology ePrint Archive: Report 2020/897

Folding BIKE: Scalable Hardware Implementation for Reconfigurable Devices

Jan Richter-Brockmann and Johannes Mono and Tim Güneysu

Abstract: Contemporary digital infrastructures and systems use and trust Public-Key Cryptography to exchange keys over insecure communication channels. With the development and progress in the research field of quantum computers, well established schemes like RSA and ECC are more and more threatened. The urgent demand to find and standardize new schemes – which are secure in a post-quantum world – was also realized by the National Institute of Standards and Technology which announced a Post-Quantum Cryptography Standardization Project in 2017. Recently, the round three candidates were announced and one of the alternate candidates is the Key Encapsulation Mechanism scheme BIKE.

In this work we investigate different strategies to efficiently implement the BIKE algorithm on Field-Programmable Gate Arrays (FPGAs). To this extend, we improve already existing polynomial multipliers, propose efficient strategies to realize polynomial inversions, and implement the Black-Gray-Flip decoder for the first time. Additionally, our implementation is designed to be scalable and generic with the BIKE specific parameters. All together, the fastest designs achieve latencies of 2.69 ms for the key generation, 0.1 ms for the encapsulation, and 1.9 ms for the decapsulation considering the first security level.

Category / Keywords: implementation / BIKE, QC-MDPC, PQC, Reconfigurable Devices, FPGA

Date: received 16 Jul 2020, last revised 26 Nov 2020

Contact author: jan richter-brockmann at rub de

Available format(s): PDF | BibTeX Citation

Note: In the updated version we added a new design for the decapsulation module and report corresponding implementation numbers.

Version: 20201126:105010 (All versions of this report)

Short URL: ia.cr/2020/897


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