In this work we investigate different strategies to efficiently implement the BIKE algorithm on Field-Programmable Gate Arrays (FPGAs). To this extend, we improve already existing polynomial multipliers, propose efficient strategies to realize polynomial inversions, and implement the Black-Gray-Flip decoder for the first time. Additionally, our implementation is designed to be scalable and generic with the BIKE specific parameters. All together, the fastest designs achieve latencies of 2.69 ms for the key generation, 0.1 ms for the encapsulation, and 1.9 ms for the decapsulation considering the first security level.
Category / Keywords: implementation / BIKE, QC-MDPC, PQC, Reconfigurable Devices, FPGA Date: received 16 Jul 2020, last revised 26 Nov 2020 Contact author: jan richter-brockmann at rub de Available format(s): PDF | BibTeX Citation Note: In the updated version we added a new design for the decapsulation module and report corresponding implementation numbers. Version: 20201126:105010 (All versions of this report) Short URL: ia.cr/2020/897