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Paper 2020/465

Domain-Oriented Masked Instruction Set Architecture for RISC-V

Pantea Kiaei and Patrick Schaumont

Abstract

An important selling point for the RISC-V instruction set is the separation between ISA and the implementation of the ISA, leading to flexibility in the design. We argue that for secure implementations, this flexibility is often a vulnerability. With a hardware attacker, the side-effects of instruction execution cannot be ignored. As a result, a strict separation between the ISA interface and implementation is undesirable. We suggest that secure ISA may require additional implementation constraints. As an example, we describe an instruction-set for the development of power side-channel resistant software.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. The First International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration 2020
Keywords
RISC-VISAembedded systems securitySCA and countermeasuresdomain-oriented masking
Contact author(s)
pantea95 @ vt edu,pschaumont @ wpi edu
History
2020-04-24: revised
2020-04-24: received
See all versions
Short URL
https://ia.cr/2020/465
License
Creative Commons Attribution
CC BY
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