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Paper 2020/1148

An Area Aware Accelerator for Elliptic Curve Point Multiplication

Malik Imran and Samuel Pagliarini and Muhammad Rashid

Abstract

This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

Metadata
Available format(s)
PDF
Category
Public-key cryptography
Publication info
Preprint. MINOR revision.
Keywords
elliptic curve cryptographypoint multiplicationMontgomery algorithmFPGAASIC
Contact author(s)
malik imran @ taltech ee,samuel pagliarini @ taltech ee,mfelahi @ uqu edu sa
History
2021-03-29: revised
2020-09-25: received
See all versions
Short URL
https://ia.cr/2020/1148
License
Creative Commons Attribution
CC BY
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