Cryptology ePrint Archive: Report 2020/1127

SideLine: How Delay-Lines (May) Leak Secrets from your SoC

Joseph Gravellier and Jean-Max Dutertre and Yannick Teglia and Philippe Loubet Moundi

Abstract: To meet the ever-growing need for performance in silicon devices, SoC providers have been increasingly relying on software-hardware cooperation. By controlling hardware resources such as power or clock management from the software, developers earn the possibility to build more flexible and power efficient applications. Despite the benefits, these hardware components are now exposed to software code and can potentially be misused as open-doors to jeopardize trusted environments, perform privilege escalation or steal cryptographic secrets. In this work, we introduce SideLine, a novel side-channel vector based on delay-line components widely implemented in high-end SoCs. After providing a detailed method on how to access and convert delay-line data into power consumption information, we demonstrate that these entities can be used to perform remote power side-channel attacks. We report experiments carried out on two SoCs from distinct vendors and we recount several core-vs-core attack scenarios in which an adversary process located in one processor core aims at eavesdropping the activity of a victim process located in another core. For each scenario, we demonstrate the adversary ability to fully recover the secret key of an OpenSSL AES running in the victim core. Even more detrimental, we show that these attacks are still practicable if the victim or the attacker program runs over an operating system.

Category / Keywords: applications / AES, side-channel, hardware, software, remote, attack, cortex-A, delay-line, delay-locked-loop, openSSL, cpa, power analysis , on-chip

Date: received 16 Sep 2020

Contact author: joseph gravellier at emse fr

Available format(s): PDF | BibTeX Citation

Version: 20200921:082024 (All versions of this report)

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