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Paper 2011/332
A depth-16 circuit for the AES S-box
Joan Boyar and Rene Peralta
Abstract
New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-box and its inverse, consisting of 63 gates.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- AESS-boxnite eld inversioncircuit complexitycircuit depth.
- Contact author(s)
- peralta @ nist gov
- History
- 2011-06-22: received
- Short URL
- https://ia.cr/2011/332
- License
-
CC BY