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Paper 2010/406

Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf

Julien Francq and Céline Thuillet

Abstract

Recent cryptanalysis on SHA-1 family has led the NIST to call for a public competition named SHA-3 Contest. Efficient implementations on various platforms are a criterion for ranking performance of all the candidates in this competition. It appears that most of the hardware architectures proposed for SHA-3 candidates are basic. In this paper, we focus on an optimized implementation of the Shabal candidate. We improve the state-of-the-art using the unfolding method. This transformation leads to unroll a part of the Shabal core. More precisely, our design can produce a throughput over 3 Gbps on Virtex-5 FPGAs, with a reasonable area usage.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
hash functions
Contact author(s)
julien francq @ eads com
History
2010-07-21: received
Short URL
https://ia.cr/2010/406
License
Creative Commons Attribution
CC BY
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