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Paper 2010/292

A Low-Area yet Performant FPGA Implementation of Shabal

Jérémie Detrey and Pierrick Gaudry and Karim Khalfallah

Abstract

In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice. According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
SHA-3Shaballow areaFPGA implementation
Contact author(s)
Jeremie Detrey @ loria fr
History
2010-09-29: revised
2010-05-17: received
See all versions
Short URL
https://ia.cr/2010/292
License
Creative Commons Attribution
CC BY
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