Cryptology ePrint Archive: Report 2010/173

Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA

Jean-Luc Beuchat and Eiji Okamoto and Teppei Yamazaki

Abstract: We propose compact architectures of the SHA-$3$ candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the $G_i$ function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks.

Category / Keywords: implementation / SHA-3, BLAKE, fully autonomous implementation, compact implementation, FPGA

Date: received 1 Apr 2010, last revised 15 Sep 2010

Contact author: jeanluc beuchat at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20100916:052935 (All versions of this report)

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