Paper 2006/371
Hardware Implementation of the $\eta_T$ Pairing in Characteristic 3
Robert Ronan and Colm o hEigeartaigh and Colin Murphy and Tim Kerins and Paulo S. L. M. Barreto
Abstract
Recently, there have been many proposals for secure and novel cryptographic protocols that are built on bilinear pairings. The $\eta_T$ pairing is one such pairing and is closely related to the Tate pairing. In this paper we consider the efficient hardware implementation of this pairing in characteristic 3. All characteristic 3 operations required to compute the pairing are outlined in detail. An efficient, flexible and reconfigurable processor for the $\eta_T$ pairing in characteristic 3 is presented and discussed. The processor can easily be tailored for a low area implementation, for a high throughput implementation, or for a balance between the two. Results are provided for various configurations of the processor when implemented over the field $\mathbb{F}_{3^{97}}$ on an FPGA. As far as we are aware, the processor returns the first characteristic 3 $\eta_T$ pairing in hardware that includes a final exponentiation to a unique value.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- $\eta_T$ pairingcharacteristic 3elliptic curvereconfigurable processorFPGA
- Contact author(s)
- robertcronan @ gmail com
- History
- 2006-11-03: received
- Short URL
- https://ia.cr/2006/371
- License
-
CC BY