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    <title>2008 Reports</title>
    <link>http://eprint.iacr.org/forum/list.php?8</link>
    <description><![CDATA[Discussion forum for Cryptology ePrint Archive reports posted in 2008.
Please put the report number in the subject.

]]></description>
    <language>EN</language>
    <pubDate>Thu, 06 May 2010 11:39:10 -0600</pubDate>
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    <item>
      <title>Question on Güneysu &amp; Paar's DSP based fast modular reduction unit</title>
      <link>http://eprint.iacr.org/forum/read.php?8,250,250#msg-250</link>
      <author>Artur</author>
      <description><![CDATA[This questions concerns the paper &quot;Ultra High Performance ECC over NIST Primes on Commercial FPGAs&quot; from CHES 2008.

Güneysu uses the reduction algorithm of Solinas for NIST (generalized Mersenne) primes P-224 and P-256 in his algorithm listings 1 and 2. In figure 5 he displays a digital circuit block diagram of the reduction chain implementing the fast modular reduction step. While Güneysu clearly implies that the diagram is meant only to show the &quot;general structure&quot; of a DSP based fast reduction circuit, it is not clear to me at all how to implement the circuit, say, for P-224.

Does anyone know the configuration of the DSPs? E.g., how do we determine when to reset and accumulate and also how do we know when and where to add in the various c_i's. (I.e., what are the mux select line configurations per cycle.) What about the carries from each 32-bit digit to the next?

Has anyone verified the results of this paper?

Best,
Artur]]></description>
      <category>2008 Reports</category>
      <guid isPermaLink="true">http://eprint.iacr.org/forum/read.php?8,250,250#msg-250</guid>
      <pubDate>Thu, 06 May 2010 11:39:10 -0600</pubDate>
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