Cryptology ePrint Archive: Report 2017/284

SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA

Maik Ender and Alexander Wild and Amir Moradi

Abstract: Side-channel analysis attacks, particularly power analysis attacks, have become one of the major threats, that hardware designers have to deal with. To defeat them, the majority of the known concepts are based on either masking, hiding, or rekeying (or a combination of them). This work deals with a hiding scheme, more precisely a power-equalization technique which is ideally supposed to make the amount of power consumption of the device independent of its processed data. We propose and practically evaluate a novel construction dedicated to Xilinx FPGAs, which rules out the state of the art with respect to the achieved security level and the resource overhead.

Category / Keywords: implementation / side-channel analysis countermeasure

Original Publication (in the same form): COSADE 2017

Date: received 28 Mar 2017

Contact author: maik ender at rub de

Available format(s): PDF | BibTeX Citation

Version: 20170330:124738 (All versions of this report)

Short URL: ia.cr/2017/284

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