Cryptology ePrint Archive: Report 2017/248

IPcore implementation susceptibility: A case study of Low latency ciphers

Dillibabu Shanmugam and Ravikumar Selvam and Suganya Annadurai

Abstract: Security evaluation of third-party cryptographic IP (Intellectual Property) cores is often ignored due to several reasons including, lack of awareness about its adversity, lack of trust validation methodology otherwise view security as a byproduct. Particularly, the validation of low latency cipher IP core on Internet of Things (IoT) devices is crucial as they may otherwise become vulnerable for information theft. In this paper, we share an (Un)intentional way of cipher implementation as IP core(hard) become susceptible against side channel attack and show how the susceptible implementation can be experimentally exploited to reveal secret key in FPGA using power analysis. In this paper our contributions are: First, we present Look-Up Table (LUT) based unrolled implementation of PRINCE block cipher with place and route constraints in FPGA. Second, using power analysis attack we recover 128-bit key of PRINCE with complexity of 2^9. Finally, we conclude the paper with the experimental results.

Category / Keywords: implementation / Side channel Attack and Low latency Cipher and Intellectual Property

Date: received 15 Mar 2017

Contact author: dillibabu at setsindia net

Available format(s): PDF | BibTeX Citation

Version: 20170320:142411 (All versions of this report)

Short URL: ia.cr/2017/248

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