Cryptology ePrint Archive: Report 2017/005

High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

Abstract: In this paper high-speed hardware architectures of point multiplication based on Montgomery ladder algorithm for binary Edwards and generalized Hessian curves in Gaussian normal basis are presented. Computations of the point addition and point doubling in the proposed architecture are concurrently performed by pipelined digit-serial finite field multipliers. The multipliers in parallel form are scheduled for lower number of clock cycles. The structure of proposed digit-serial Gaussian normal basis multiplier is constructed based on regular and low-cost modules of exponentiation by powers of two and multiplication by normal elements. Therefore, the structures are area efficient and have low critical path delay. Implementation results of the proposed architectures on Virtex-5 XC5VLX110 FPGA show that then execution time of the point multiplication for binary Edwards and generalized Hessian curves over GF(2163) and GF(2233) are 8.62Ás and 11.03Ás respectively. The proposed architectures have high-performance and high-speed compared to other works.

Category / Keywords: implementation /

Date: received 5 Jan 2017

Contact author: b_rashidi86 at yahoo com

Available format(s): PDF | BibTeX Citation

Version: 20170111:130449 (All versions of this report)

Short URL: ia.cr/2017/005

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