Cryptology ePrint Archive: Report 2016/969

Garbling Gadgets for Boolean and Arithmetic Circuits

Marshall Ball and Tal Malkin and Mike Rosulek

Abstract: We present simple, practical, and powerful new techniques for garbled circuits. These techniques result in significant concrete and asymptotic improvements over the state of the art, for several natural kinds of computations.

For arithmetic circuits over the integers, our construction results in garbled circuits with {\em free} addition, weighted threshold gates with cost independent of fan-in, and exponentiation by a fixed exponent with cost independent of the exponent. For boolean circuits, our construction gives an {\em exponential} improvement over the state of the art for threshold gates (including AND/OR gates) of high fan-in.

Our construction can be efficiently instantiated with practical symmetric-key primitives (e.g., AES), and is proven secure under similar assumptions to that of the Free-XOR garbling scheme (Kolesnikov \& Schneider, ICALP 2008). We give an extensive comparison between our scheme and state-of-the-art garbling schemes applied to boolean circuits.

Category / Keywords: cryptographic protocols / garbled circuits, secure computation, arithmetic circuits

Original Publication (with minor differences): ACM CCS 2016
DOI:
10.1145/2976749.2978410

Date: received 6 Oct 2016

Contact author: rosulekm at eecs oregonstate edu

Available format(s): PDF | BibTeX Citation

Version: 20161010:150534 (All versions of this report)

Short URL: ia.cr/2016/969

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