Cryptology ePrint Archive: Report 2016/927

Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core

Subhadeep Banik and Andrey Bogdanov and Francesco Regazzoni

Abstract: The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and decryption (ENC/DEC) while keeping the hardware overhead as low as possible. As a result, we report an 8-bit serialized AES circuit that provides the functionality of both encryption and decryption and occupies around 2645 GE with a latency of 226 cycles. This is a substantial improvement over the next smallest AES ENC/DEC circuit (Grain of Sand) by Feldhofer et al. which takes around 3400 gates but has a latency of over 1000 cycles for both the encryption and decryption cycles.

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Original Publication (with minor differences): Indocrypt 2016

Date: received 24 Sep 2016

Contact author: bsubhadeep at ntu edu sg

Available format(s): PDF | BibTeX Citation

Version: 20160924:221450 (All versions of this report)

Short URL: ia.cr/2016/927

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