Cryptology ePrint Archive: Report 2016/522

A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version)

Daisuke Fujimoto and Shivam Bhasin and Makoto Nagata and Jean-Luc Danger

Abstract: Testing of electronic components is indispensable to minimize malfunction and failure of complex electronic systems. Currently, functionality and performance of these electronic components are the main parameters tested. However, validation of performance is not enough when the applications are safety or security critical. Therefore the security and trust of devices must also be tested before validation for such applications. In this paper, we promote the use of On-Chip Power noise Measurements (OCM), in order to test security using side-channel techniques. We then propose for the first time a standard side-channel measurement setup using OCM. Finally, we provide some key ideas on methodology to integrate the validation of hardware security and trust in the standard testing flow, exploiting OCM.

Category / Keywords: applications / security, trust, standardised side-channel measurement, hardware trojan

Original Publication (with minor differences): The 20th Asia and South Pacific Design Automation Conference
DOI:
10.1109/ASPDAC.2015.7059100

Date: received 27 May 2016

Contact author: sbhasin at ntu edu sg

Available format(s): PDF | BibTeX Citation

Version: 20160529:210652 (All versions of this report)

Short URL: ia.cr/2016/522

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