Cryptology ePrint Archive: Report 2016/441

Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA

Durga Prasad Sahoo and Sikhar Patranabis and Debdeep Mukhopadhyay and Rajat Subhra Chakraborty

Abstract: Recent literature has demonstrated that the security of Physically Unclonable Function (PUF) circuits might be adversely affected by the introduction of faults. In this paper, we propose novel and efficient architectures for a variety of widely used delay-based PUFs which are robust against high precision laser fault attacks proposed by Tajik et al. in FDTC-2015. The proposed architectures can be used to detect run-time modifications in the PUF design due to fault injection. In addition, we propose fault recovery techniques based on either logical reconfiguration or dynamic partial reconfiguration of the PUF design. We validate the robustness of our proposed fault tolerant delay-based PUF designs on Xilinx Artix-7 FPGA platform.

Category / Keywords: implementation / Arbiter PUF (APUF), PUF, laser fault attacks and countermeasures, robust PUF architectures.

Date: received 3 May 2016

Contact author: dpsahoo cs at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20160504:093816 (All versions of this report)

Short URL: ia.cr/2016/441

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