Cryptology ePrint Archive: Report 2016/1111

Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware

Pascal Sasdrich and Amir Moradi and Tim GŁneysu

Abstract: First-order secure Threshold Implementations (TI) of symmetric cryptosystems provide provable security at a moderate overhead; yet attacks using higher-order statistical moments are still feasible. Cryptographic instances compliant to Higher-Order Threshold Implementation (HO-TI) can prevent such attacks, however, usually at unacceptable implementation costs. As an alternative concept we investigate in this work the idea of dynamic hardware modification, i.e., random changes and transformations of cryptographic implementations in order to render higher-order attacks on first-order TI impractical. In a first step, we present a generic methodology which can be applied to (almost) every cryptographic implementation. In order to investigate the effectiveness of our proposed strategy, we use an instantiation of our methodology that adapts ideas from White-Box Cryptography and applies this construction to a first-order secure TI. Further, we show that dynamically updating cryptographic implementations during operation provides the ability to avoid higher-order leakages to be practically exploitable.

Category / Keywords: implementation / side-channel protection, TI, FPGA, WBC, dynamic hardware modification

Original Publication (in the same form): CT-RSA 2017

Date: received 24 Nov 2016

Contact author: pascal sasdrich at rub de

Available format(s): PDF | BibTeX Citation

Version: 20161125:141329 (All versions of this report)

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