Cryptology ePrint Archive: Report 2016/1005

Atomic-AES v2.0

Subhadeep Banik and Andrey Bogdanov and Francesco Regazzoni

Abstract: Very recently, the {\sf Atomic AES} architecture that provides dual functionality of the AES encryption and decryption module was proposed. It was surprisingly compact and occupied only around 2605 GE of silicon area and took 226 cycles for both the encryption and decryption operations. In this work we further optimize the above architecture to provide the dual encryption/decryption functionality in only 2060 GE and latency of 246/326 cycles for the encryption and decryption operations respectively. We take advantage of clock gating techniques to achieve Shiftrow and Inverse Shiftrow operations in 3 cycles instead of 1. This helps us replace many of the scan flip-flops in the design with ordinary flip-flops. Furthermore we take advantage of the fact that the Inverse Mixcolumn matrix in AES is the cube of the forward Mixcolumn matrix. Thus by executing the forward Mixcolumn operation three times over the state, one can achieve the functionality of Inverse Mixcolumn. This saves some more gate area as one is no longer required to have a combined implementation of the Forward and Inverse Mixcolumn circuit.

Category / Keywords: AES 128, Serialized Implementation

Date: received 22 Oct 2016, last revised 16 Mar 2017

Contact author: bsubhadeep at ntu edu sg

Available format(s): PDF | BibTeX Citation

Version: 20170316:161956 (All versions of this report)

Short URL: ia.cr/2016/1005

Discussion forum: Show discussion | Start new discussion


[ Cryptology ePrint archive ]