Cryptology ePrint Archive: Report 2015/974

The Conjoined Microprocessor

Ehsan Aerabi and A. Elhadi Amirouche and Houda Ferradi and Rémi Géraud David Naccache and Jean Vuillemin

Abstract: Over the last twenty years, the research community has devised sophisticated methods for retrieving secret information from sidechannel emanations, and for resisting such attacks. This paper introduces a new CPU architecture called the Conjoined Microprocessor. The Conjoined Microprocessor can randomly interleave the execution of two programs at very low extra hardware cost. We developed for the Conjoined Microprocessor a preprocessor tool that turns a target algorithm into two (or more) separate queues like $Q_0$ and $Q_1$ that can run in alternation. $Q_0$ and $Q_1$ fulfill the same operation as the original target algorithm. Power-analysis resistance is achieved by randomly alternating the execution of $Q_0$ and $Q_1$, with different runs resulting in different interleavings. Experiments reveal that this architecture is indeed effective against CPA.

Category / Keywords: implementation / side channel attacks

Date: received 7 Oct 2015, last revised 9 Oct 2015

Contact author: david naccache at ens fr

Available format(s): PDF | BibTeX Citation

Version: 20151011:025352 (All versions of this report)

Short URL: ia.cr/2015/974

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