The Conjoined Microprocessor

Ehsan Aerabi; A.  Elhadi Amirouche; Houda Ferradi; Rémi Géraud; David Naccache; Jean Vuillemin

Paper 2015/974

The Conjoined Microprocessor

Ehsan Aerabi, A. Elhadi Amirouche, Houda Ferradi, Rémi Géraud, David Naccache, and Jean Vuillemin

Abstract

Over the last twenty years, the research community has devised sophisticated methods for retrieving secret information from sidechannel emanations, and for resisting such attacks. This paper introduces a new CPU architecture called the Conjoined Microprocessor. The Conjoined Microprocessor can randomly interleave the execution of two programs at very low extra hardware cost. We developed for the Conjoined Microprocessor a preprocessor tool that turns a target algorithm into two (or more) separate queues like $Q_0$ and $Q_1$ that can run in alternation. $Q_0$ and $Q_1$ fulfill the same operation as the original target algorithm. Power-analysis resistance is achieved by randomly alternating the execution of $Q_0$ and $Q_1$, with different runs resulting in different interleavings. Experiments reveal that this architecture is indeed effective against CPA.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint. MINOR revision.
Keywords: side channel attacks
Contact author(s): david naccache @ ens fr
History: 2015-10-11: received
Short URL: https://ia.cr/2015/974
License: CC BY

BibTeX

@misc{cryptoeprint:2015/974,
      author = {Ehsan Aerabi and A.  Elhadi Amirouche and Houda Ferradi and Rémi Géraud and David Naccache and Jean Vuillemin},
      title = {The Conjoined Microprocessor},
      howpublished = {Cryptology {ePrint} Archive, Paper 2015/974},
      year = {2015},
      url = {https://eprint.iacr.org/2015/974}
}