Cryptology ePrint Archive: Report 2015/786
Buying AES Design Resistance with Speed and Energy
Jean-Michel Cioranesco and Roman Korkikian and David Naccache and Rodrigo Portella do Canto
Abstract: Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AESí algorithmic features to propose low-cost and low-latency protections.
We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the userís needs and the systemís constraints.
Category / Keywords: implementation / side channel attacks, fault attacks, AES
Date: received 6 Aug 2015, last revised 10 Aug 2015
Contact author: david naccache at ens fr
Available format(s): PDF | BibTeX Citation
Version: 20150810:071922 (All versions of this report)
Short URL: ia.cr/2015/786
Discussion forum: Show discussion | Start new discussion
[ Cryptology ePrint archive ]