Cryptology ePrint Archive: Report 2015/744

BitCryptor: Bit-Serialized Compact Crypto Engine on Reconfigurable Hardware

Ege Gulcan and Aydin Aysu and Patrick Schaumont

Abstract: There is a significant effort in building lightweight cryptographic operations, yet the proposed solutions are typically single-purpose modules that can implement a single functionality. In contrast, we propose BitCryptor, a multi-purpose, bit-serialized compact processor for cryptographic applications on reconfigurable hardware. The proposed crypto engine can perform pseudo-random number generation, strong collision-resistant hashing and variable-key block cipher encryption. The hardware architecture utilizes SIMON, a recent lightweight block cipher, as its core. The complete engine uses a bit-serial design methodology to minimize the area. Implementation results on the Xilinx Spartan-3 s50 FPGA show that the proposed architecture occupies 95 slices (187 LUTs, 102 registers), which is 10$\times$ smaller than the nearest comparable multi-purpose design. BitCryptor is also smaller than the majority of recently proposed lightweight single-purpose designs. Therefore, it is a very efficient cryptographic IP block for resource-constrained domains, providing a good performance at a minimal area overhead.

Category / Keywords: implementation / Lightweight cryptography, bit-serialization, hardware architecture, crypto engine, SIMON, FPGA

Date: received 23 Jul 2015

Contact author: aydinay at vt edu

Available format(s): PDF | BibTeX Citation

Version: 20150724:125241 (All versions of this report)

Short URL: ia.cr/2015/744

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