Paper 2015/294
Accelerating Somewhat Homomorphic Evaluation using FPGAs
Erdi̇̀nç Öztürk, Yarkın Doröz, Berk Sunar, and Erkay Savaş
Abstract
After being introduced in 2009, the first fully homomorphic encryption (FHE) scheme has created significant excitement in academia and industry. Despite rapid advances in the last 6 years, FHE schemes are still not ready for deployment due to an efficiency bottleneck. Here we introduce a custom hardware accelerator optimized for a class of reconfigurable logic to bring LTV based somewhat homomorphic encryption (SWHE) schemes one step closer to deployment in real-life applications. The accelerator we present is connected via a fast PCIe interface to a CPU platform to provide homomorphic evaluation services to any application that needs to support blinded computations. Specifically we introduce a number theoretical transform based multiplier architecture capable of efficiently handling very large polynomials. When synthesized for the Xilinx Virtex 7 family the presented architecture can compute the product of large polynomials in under
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Preprint. MINOR revision.
- Keywords
- Homomorphic encryptionNTT multiplicationFPGA
- Contact author(s)
- sunar @ wpi edu
- History
- 2015-04-01: received
- Short URL
- https://ia.cr/2015/294
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2015/294, author = {Erdi̇̀nç Öztürk and Yarkın Doröz and Berk Sunar and Erkay Savaş}, title = {Accelerating Somewhat Homomorphic Evaluation using {FPGAs}}, howpublished = {Cryptology {ePrint} Archive, Paper 2015/294}, year = {2015}, url = {https://eprint.iacr.org/2015/294} }