Cryptology ePrint Archive: Report 2015/294

Accelerating Somewhat Homomorphic Evaluation using FPGAs

Erdinç Öztürk and Yarkın Doröz and Berk Sunar and Erkay Savaş

Abstract: After being introduced in 2009, the first fully homomorphic encryption (FHE) scheme has created significant excitement in academia and industry. Despite rapid advances in the last 6 years, FHE schemes are still not ready for deployment due to an efficiency bottleneck. Here we introduce a custom hardware accelerator optimized for a class of reconfigurable logic to bring LTV based somewhat homomorphic encryption (SWHE) schemes one step closer to deployment in real-life applications. The accelerator we present is connected via a fast PCIe interface to a CPU platform to provide homomorphic evaluation services to any application that needs to support blinded computations. Specifically we introduce a number theoretical transform based multiplier architecture capable of efficiently handling very large polynomials. When synthesized for the Xilinx Virtex 7 family the presented architecture can compute the product of large polynomials in under $6.25$~msec making it the fastest multiplier design of its kind currently available in the literature and is more than 102 times faster than a software implementation. Using this multiplier we can compute a relinearization operation in $526$ msec. When used as an accelerator, for instance, to evaluate the AES block cipher, we estimate a per block homomorphic evaluation performance of $442$~msec yielding performance gains of $28.5$ and $17$ times over similar CPU and GPU implementations, respectively.

Category / Keywords: implementation / Homomorphic encryption, NTT multiplication, FPGA

Date: received 28 Mar 2015

Contact author: sunar at wpi edu

Available format(s): PDF | BibTeX Citation

Version: 20150401:134525 (All versions of this report)

Short URL: ia.cr/2015/294

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