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Paper 2015/200

Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs

Alexander Wild and Amir Moradi and Tim Güneysu

Abstract

Power-equalization schemes for digital circuits aim to harden cryptographic designs against power analysis attacks. With respect to dual-rail logics most of these schemes have originally been designed for ASIC platforms, but much efforts have been spent to map them to FPGAs as well. A particular challenge is here to apply those schemes to the predefined logic structures of FPGAs (i.e., slices, LUTs, FFs, and routing switch boxes) for which special tools are required. Due to the absence of such routing tools Yu and Schaumont presented the idea of duplicating (i.e., dualizing) a fully-placed-and-routed dual-rail precharge circuit with equivalent routing structures on an FPGA. They adopted such architecture from WDDL providing the Double WDDL (DWDDL)scheme. In this work we show that this general technique - regardless of the underlying dual-rail logic - is incapable to properly prevent side-channel leakages. Besides theoretical investigations on this issue we present practical evaluations on a Spartan-6 FPGA to demonstrate the flaws in such an approach. In detail, we consider an AES-128 encryption module realized by three dual-rail precharge logic styles as a case study and show that none of those schemes can provide the desired level of protection.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. COSADE 2015
Keywords
side-channel analysiscountermeasureFPGADPA-resistant logic styleDWDDL
Contact author(s)
amir moradi @ rub de
History
2015-03-04: received
Short URL
https://ia.cr/2015/200
License
Creative Commons Attribution
CC BY
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