Cryptology ePrint Archive: Report 2015/1252

Improved Test Pattern Generation for Hardware Trojan Detection using Genetic Algorithm and Boolean Satisfiability

Sayandeep Saha and Rajat Subhra Chakraborty and Srinivasa Shashank Nuthakki and Anshul and Debdeep Mukhopadhyay

Abstract: Test generation for \emph{Hardware Trojan Horses} (HTH) detection is extremely challenging, as Trojans are designed to be triggered by very rare logic conditions at internal nodes of the circuit. In this paper, we propose a \textit{Genetic Algorithm} (GA) based Automatic Test Pattern Generation (ATPG) technique, enhanced by automated solution to an associated \textit{Boolean Satisfiability} problem. The main insight is that given a specific internal trigger condition, it is not possible to attack an arbitrary node (payload) of the circuit, as the effect of the induced logic malfunction by the HTH might not get propagated to the output. Based on this observation, a fault simulation based framework has been proposed, which enumerates the feasible payload nodes for a specific triggering condition. Subsequently, a compact set of test vectors is selected based on their ability to detect the logic malfunction at the feasible payload nodes, thus increasing their effectiveness. Test vectors generated by the proposed scheme were found to achieve higher detection coverage over large population of HTH in ISCAS benchmark circuits, compared to a previously proposed logic testing based Trojan detection technique.

Category / Keywords: applications / Hardware Trojans, Genetic Algorithm, Boolean Satisfiability

Original Publication (with minor differences): IACR-CHES-2015

Date: received 1 Jan 2016

Contact author: sahasayandeep91 at gmail com

Available format(s): PDF | BibTeX Citation

Note: This paper has already been published in CHES 2015. Here are some minor revisions of the manuscript.

Version: 20160102:212139 (All versions of this report)

Short URL: ia.cr/2015/1252

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