Cryptology ePrint Archive: Report 2015/124

GliFreD: Glitch-Free Duplication - Towards Power-Equalized Circuits on FPGAs

Alexander Wild and Amir Moradi and Tim GŁneysu

Abstract: Designers of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits are required to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure poses a particular challenge. In this work, we propose and practically evaluate a new DRP scheme (GliFreD) that has been exclusively designed for FPGA platforms. GliFreD overcomes the well-known early propagation issue, prevents glitches, uses an isolated dual-rail concept, and mitigates imbalanced routings. With all these features, GliFreD significantly exceeds the level of physical security achieved by any previously reported, related countermeasures for FPGAs.

Category / Keywords: implementation / side-channel protection, FPGA, hiding, power equalization

Date: received 17 Feb 2015, last revised 4 Mar 2015

Contact author: amir moradi at rub de

Available format(s): PDF | BibTeX Citation

Version: 20150304:104415 (All versions of this report)

Short URL: ia.cr/2015/124

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