Cryptology ePrint Archive: Report 2015/1172

An Application Specific Instruction Set Processor (ASIP) for the Niederreiter Cryptosystem

Jingwei Hu and Ray C.C. Cheung

Abstract: The Niederreiter public-key cryptosystem is based on the security assumption that decoding generic linear binary codes is NP complete, and therefore, is regarded as an alternative post-quantum solution to resist quantum computing. Current hardware implementations for the Niederreiter cryptosystem focus on data encryption/decryption but few of them consider digital signature producing given that signature scheme is much different from encrytion/decrytion and complicated to be integrated. In this work, we address the problem of achieving efficient Niederreiter digital signature and extending it to execute encryption/decryption on reconfigurable hardware. We first present a new parameter selection method by which both encryption/decryption and signature are able to be performed with the same hardware configurations. Then we design a compact ASIP architecture with the proposed parameter selection and resource sharing elaboration. FGPA experiments show that the proposed unified architecture can achieve encryption, decryption and signature with $1.41~\mu s$, $798.57~\mu s$ and $14.07~s$ respectively while maintaining acceptable area tradeoffs ($4254\times$slices, $29\times$36Kb-BRAMs and $3\times$DSP48E1s) on Virtex-6 devices.

Category / Keywords: implementation / Cryptographic hardware and implementation, Application Specific Instruction Set Processor, Niederreiter cryptosystem, FPGA.

Date: received 6 Dec 2015, withdrawn 23 Mar 2016

Contact author: davidhoo471494221 at gmail com

Available format(s): (-- withdrawn --)

Version: 20160324:021551 (All versions of this report)

Short URL: ia.cr/2015/1172

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