Efficient Pairings and ECC for Embedded Systems

Thomas Unterluggauer; Erich Wenger

Paper 2014/800

Efficient Pairings and ECC for Embedded Systems

Thomas Unterluggauer and Erich Wenger

Abstract

The research on pairing-based cryptography brought forth a wide range of protocols interesting for future embedded applications. One significant obstacle for the widespread deployment of pairing-based cryptography are its tremendous hardware and software requirements. In this paper we present three side-channel protected hardware/software designs for pairing-based cryptography yet small and practically fast: our plain ARM Cortex-M0+-based design computes a pairing in less than one second. The utilization of a multiply-accumulate instruction-set extension or a light-weight drop-in hardware accelerator that is placed between CPU and data memory improves runtime up to six times. With a 10.1 kGE large drop-in module and a 49 kGE large platform, our design is one of the smallest pairing designs available. Its very practical runtime of 162 ms for one pairing on a 254-bit BN curve and its reusability for other elliptic-curve based crypto systems offer a great solution for every microprocessor-based embedded application.

Note: Added footnote reference to published source code at https://github.com/IAIK/pairings_in_c.

Metadata

Available format(s): PDF
Publication info: A minor revision of an IACR publication in CHES 2014
Keywords: implementation
Contact author(s): thomas unterluggauer @ iaik tugraz at
History: 2015-09-23: revised; 2014-10-10: received; See all versions
Short URL: https://ia.cr/2014/800
License: CC BY

BibTeX

@misc{cryptoeprint:2014/800,
      author = {Thomas Unterluggauer and Erich Wenger},
      title = {Efficient Pairings and {ECC} for Embedded Systems},
      howpublished = {Cryptology {ePrint} Archive, Paper 2014/800},
      year = {2014},
      url = {https://eprint.iacr.org/2014/800}
}