Cryptology ePrint Archive: Report 2014/750
Hardware Trojan Horses in Cryptographic IP Cores
Shivam Bhasin and Jean-Luc Danger and Sylvain Guilley and Xuan Thuy Ngo and Laurent Sauvage
Abstract: Detecting hardware trojans is a difficult task in general.
In this article we study hardware trojan horses insertion and detection in cryptographic intellectual property (IP) blocks.
The context is that of a fabless design house that sells IP blocks as GDSII hard macros, and wants to check that final products have not been infected by trojans during the foundry stage.
First, we show the efficiency of a medium cost hardware trojans detection method if the placement or the routing have been redone by the foundry.
It consists in the comparison between optical microscopic pictures of the silicon product and the original view from a GDSII layout database reader.
Second, we analyze the ability of an attacker to introduce a hardware trojan horse without changing neither the placement nor the routing of the cryptographic IP logic.
On the example of an AES engine, we show that if the placement density is beyond $80$\%, the insertion is basically impossible.
Therefore, this settles a simple design guidance to avoid trojan horses insertion in cryptographic IP blocks:
have the design be compact enough, so that any functionally discreet trojan necessarily requires a complete re-place and re-route, which is detected by mere optical imaging (and not complete chip reverse-engineering).
Category / Keywords: implementation /
Original Publication (with minor differences): FDTC 2013
Date: received 26 Sep 2014
Contact author: sylvain guilley at telecom-paristech fr
Available format(s): PDF | BibTeX Citation
Note: In this revision, we explain how to design a hardware trojan horse that is triggered only by specially crafted inputs (plaintexts or ciphertexts).
Version: 20140929:082939 (All versions of this report)
Short URL: ia.cr/2014/750
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