Cryptology ePrint Archive: Report 2014/734

S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go?

Lejla Batina and Domagoj Jakobovic and Nele Mentens and Stjepan Picek and Antonio de la Piedra and Dominik Sisejkovic

Abstract: In the last few years, several practitioners have proposed a wide range of approaches for reducing the implementation area of the AES in hardware. However, an area-throughput trade-off that undermines high-speed is not realistic for real-time cryptographic applications. In this manuscript, we explore how Genetic Algorithms (GAs) can be used for pipelining the AES substitution box based on composite field arithmetic. We implemented a framework that parses and analyzes a Verilog netlist, abstracts it as a graph of interconnected cells and generates circuit statistics on its elements and paths. With this information, the GA extracts the appropriate arrangement of Flip-Flops (FFs) that maximizes the throughput of the given netlist. In doing so, we show that it is possible to achieve a 50 % improvement in throughput with only an 18 % increase in area in the UMC 0.13 um low-leakage standard cell library.

Category / Keywords: implementation / AES S-BOX, Genetic Algorithms, ASIC

Original Publication (in the same form): INDOCRYPT 2014

Date: received 19 Sep 2014, last revised 19 Sep 2014

Contact author: a delapiedra at cs ru nl

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Version: 20140919:212359 (All versions of this report)

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