Cryptology ePrint Archive: Report 2014/649

FPGA Trojans through Detecting and Weakening of Cryptographic Primitives

Pawel Swierczynski and Marc Fyrbiak and Philipp Koppe and Christof Paar

Abstract: This paper investigates a novel attack vector against cryptography realized on FPGAs, which poses a serious threat to real-world applications.We demonstrate how a targeted bitstream modification can seriously weaken cryptographic algorithms, which we show with the examples of AES and 3DES. The attack is performed by modifying the FPGA bitstream that configures the hardware elements during initialization. Recently, it has been shown that cloning of FPGA designs is feasible, even if the bitstream is encrypted. However, due to its proprietary file format, a meaningful modification is very challenging. While some previous work addressed bitstream reverse-engineering, so far it has not been evaluated how difficult it is to detect and modify cryptographic elements. We outline two possible practical attacks that have serious security implications. We target the S-boxes of block ciphers that can be implemented in look-up tables or stored as precomputed set of values in the memory of the FPGA. We demonstrate that it is possible to detect and apply meaningful changes to cryptographic elements inside an unknown, proprietary and undocumented bitstream. Our proposed attack does not require any knowledge of the internal routing. Furthermore, we show how an AES key can be revealed within seconds. Finally, we discuss countermeasures that can raise the bar for an adversary to successfully perform this kind of attack.

Category / Keywords: Hardware security, FPGAs, Trojans, bitstream manipulation, reverse-engineering, DES, AES.

Date: received 21 Aug 2014, last revised 18 Dec 2014

Contact author: pawel swierczynski at rub de

Available format(s): PDF | BibTeX Citation

Version: 20141218:191832 (All versions of this report)

Short URL: ia.cr/2014/649

Discussion forum: Show discussion | Start new discussion