Optimized Architecture for AES

Abhijith P.  S; Dr.  Manish Goswami; S.  Tadi; Kamal Pandey

Paper 2014/540

Optimized Architecture for AES

Abhijith P. S, Dr. Manish Goswami, S. Tadi, and Kamal Pandey

Abstract

This paper presents a highly optimized architecture for Advanced Encryption Standard (AES) by dividing and merging (combining) different sub operations in AES algorithm. The proposed architecture uses ten levels of pipelining to achieve higher throughput and uses Block-RAM utility to reduce slice utilization which subsequently increases the efficiency. It achieves the data stream of 57 Gbps at 451 MHz working frequency and obtains 36% improvement in efficiency to the best known similar design throughput per area (Throughput/Area) and 35% smaller in slice area. This architecture can easily be embedded with other modules because of significantly reduced slice utilization.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint. MINOR revision.
Keywords: Advanced Encryption Standard (AES)Composite Field Arithmetic Field Programmable Gate Array (FPGA)
Contact author(s): mgoswami005 @ gmail com
History: 2014-07-18: received
Short URL: https://ia.cr/2014/540
License: CC BY

BibTeX

@misc{cryptoeprint:2014/540,
      author = {Abhijith P.  S and Dr.  Manish Goswami and S.  Tadi and Kamal Pandey},
      title = {Optimized Architecture for {AES}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2014/540},
      year = {2014},
      url = {https://eprint.iacr.org/2014/540}
}