Cryptology ePrint Archive: Report 2014/540

Optimized Architecture for AES

Abhijith P. S and Dr. Manish Goswami and S. Tadi and Kamal Pandey

Abstract: This paper presents a highly optimized architecture for Advanced Encryption Standard (AES) by dividing and merging (combining) different sub operations in AES algorithm. The proposed architecture uses ten levels of pipelining to achieve higher throughput and uses Block-RAM utility to reduce slice utilization which subsequently increases the efficiency. It achieves the data stream of 57 Gbps at 451 MHz working frequency and obtains 36% improvement in efficiency to the best known similar design throughput per area (Throughput/Area) and 35% smaller in slice area. This architecture can easily be embedded with other modules because of significantly reduced slice utilization.

Category / Keywords: implementation / Advanced Encryption Standard (AES), Composite Field Arithmetic, Field Programmable Gate Array (FPGA)

Date: received 11 Jul 2014

Contact author: mgoswami005 at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20140718:070436 (All versions of this report)

Short URL: ia.cr/2014/540

Discussion forum: Show discussion | Start new discussion