Cryptology ePrint Archive: Report 2014/497

NREPO:Normal Basis Recomputing with Permuted Operands

Xiaofei Guo , Debdeep Mukhopadhyay , Chenglu Jin and Ramesh Karri

Abstract: Hardware implementations of cryptographic algorithms are vulnerable to natural and malicious faults. Concurrent Error Detection (CED) can be used to detect these faults. We present NREPO, a CED which does not require redundant computational resources in the design. Therefore, one can integrate it when computational resources are scarce or when the redundant resources are difficult to harness for CED. We integrate NREPO in a low-cost Advanced Encryption Standard (AES) implementation with 8-bit datapath. We show that NREPO has 25 and 50 times lower fault miss rate than robust code and parity, respectively. The area, throughput, and power are compared with other CEDs on 45nm ASIC. The hardware overhead of NREPO is 34.9%. The throughput and power are 271.6Mbps and 1579.3μW , respectively. One can also implement NREPO in other cryptographic algorithms.

Category / Keywords: implementation / fault attack, error detection, testing

Original Publication (with minor differences): IEEE Int. Symposium on Hardware-Oriented Security and Trust

Date: received 22 Jun 2014, last revised 5 Sep 2015

Contact author: xiaofei guo rex at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20150905:164406 (All versions of this report)

Short URL: ia.cr/2014/497

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