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Paper 2014/454

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

Amir Moradi and Vincent Immler

Abstract

This work deals with DPA-resistant logic styles, i.e., cell-level countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that - if not considered during the design process - can cause the underlying cryptographic device to be vulnerable to certain attacks. Although most of the DPA-resistant logic styles target an ASIC design process, there are a few attempts to apply them in an FPGA platform. This is due to the missing freedom in FPGA design tools required to deal with the aforementioned problems. Our contribution in this work is to provide solutions for both early propagation and imbalanced routings considering a modern Xilinx FPGA as the target platform. Foremost, based on the WDDL concept we design a new FPGA-based logic style without early propagation in both precharge and evaluation phases. Additionally, with respect to the limited routing resources within an FPGA we develop a customized router to nd the best appropriate dual-rail routes for a given dual-rail circuit. Based on practical experiments on a Virtex-5 FPGA our evaluations verify the efficiency of each of our proposed approaches. They significantly improve the resistance of the design compared to cases not benefiting from our schemes.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published by the IACR in CHES 2014
Keywords
side-channel analysisDPA countermeasuredual-rail precharge logicWDDLFPGA
Contact author(s)
amir moradi @ rub de
History
2016-04-04: revised
2014-06-15: received
See all versions
Short URL
https://ia.cr/2014/454
License
Creative Commons Attribution
CC BY
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