Phatak’s preliminary analysis indicates that under reasonable assumptions about hardware capabilities, a single modular multiplication’s (or QFS’s) execution time grows logarithmically with respect to the operand word length. We experimentally confirmed this predicted growth rate of the delay of a modular multiplication with our FPGA implementation. Though our implementation did not outperform the most recent implementations such as that by Gandino, et al., we determined that this outcome was solely a consequence of tradeoffs stemming from our decision to store the lookup tables on the FPGA.
Category / Keywords: implementation / Reduced-Precision Residue Number System, Residue Number System (RNS), modular exponentiation, Quotient-First Scaling (QFS) algorithm, computer arithmetic, FPGA hardware Date: received 18 Dec 2014 Contact author: cn1 at umbc edu Available format(s): PDF | BibTeX Citation Note: We hope this preliminary work will be helpful to anyone wishing to carry out another implementation of this promising method. Version: 20141225:140522 (All versions of this report) Short URL: ia.cr/2014/1009 Discussion forum: Show discussion | Start new discussion