Cryptology ePrint Archive: Report 2014/025

Side-Channel Leakage through Static Power – Should We Care about in Practice? –

Amir Moradi

Abstract: By shrinking the technology static power consumption of CMOS circuits is becoming a major concern. In this paper, we present the first practical results of exploiting static power consumption of FPGA-based cryptographic devices in order to mount a key-recovery side-channel attack. The experiments represented here are based on three Xilinx FPGAs built on 65nm, 45nm, and 28nm process technologies. By means of a sophisticated measurement setup and methodology we demonstrate an exploitable information leakage through static power of the underlying FPGAs. The current work highlights the feasibility of side-channel analysis attacks by static power that have been known for years but have not been performed and investigated in practice yet. This is a starting point for further research investigations, and may have a significant impact on the efficiency of DPA countermeasures in the near future.

Category / Keywords: implementation / Side-Channel Analysis, Staic Power Consumption

Original Publication (with minor differences): IACR-CHES-2014

Date: received 8 Jan 2014, last revised 8 Jul 2014

Contact author: amir moradi at rub de

Available format(s): PDF | BibTeX Citation

Version: 20140708:124601 (All versions of this report)

Short URL: ia.cr/2014/025

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