Paper 2013/005

Efficient Multiplier for pairings over Barreto-Naehrig Curves on Virtex-6 FPGA

Riadh Brinci, Walid Khmiriy, Mefteh Mbarekz, Abdellatif Ben Rabaˆa, Ammar Bouallegue, and Faouzi Chekir

Abstract

This paper is devoted to the design of a 258- bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five,65 bit signed integer, coefficients . Exploiting this splitting we designed a pipelined 65-bit multiplier based on new Karatsuba-Ofman variant using non-standard splitting to fit to the Xilinx embedded digital signal processor (DSP) blocks. Our architecture is able to compute 258-bit multiplication suitable for BN curves using only 11 in-built DSP blocks available on Virtex-6 Xilinx FPGA devices. It is the least DSP blocks consumption in the known literature. This work can be extended to efficiently compute pairings at higher security levels.

Metadata
Available format(s)
PDF
Publication info
Published elsewhere. Unknown where it was published
Keywords
Modular MultiplicationModular ReductionCryptographyPairing-Friendly CurvesNon-Standard SplittingField Programmable Gate Array(FPGA).
Contact author(s)
wkhmiri @ yahoo fr
History
2013-01-11: received
Short URL
https://ia.cr/2013/005
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2013/005,
      author = {Riadh Brinci and Walid Khmiriy and Mefteh Mbarekz and Abdellatif Ben Rabaˆa and Ammar Bouallegue and Faouzi Chekir},
      title = {Efficient Multiplier for pairings over Barreto-Naehrig Curves on Virtex-6 FPGA},
      howpublished = {Cryptology ePrint Archive, Paper 2013/005},
      year = {2013},
      note = {\url{https://eprint.iacr.org/2013/005}},
      url = {https://eprint.iacr.org/2013/005}
}
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