Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs

Kris Gaj; Ekawat Homsirikamol; Marcin Rogawski; Rabia Shahid; Malik Umar Sharif

Paper 2012/368

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, and Malik Umar Sharif

Abstract

In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of iteration, folding, unrolling, pipelining, and circuit replication. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance in FPGAs. The characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.

Note: Minor revision of Table 7 and Fig. 10.

Metadata

Available format(s): PDF
Publication info: Published elsewhere. initial version presented at the Third SHA-3 Candidate Conference
Keywords: benchmarking hash functions SHA-3 hardware FPGA
Contact author(s): kgaj @ gmu edu
History: 2012-10-31: last of 2 revisions; 2012-06-29: received; See all versions
Short URL: https://ia.cr/2012/368
License: CC BY

BibTeX

@misc{cryptoeprint:2012/368,
      author = {Kris Gaj and Ekawat Homsirikamol and Marcin Rogawski and Rabia Shahid and Malik Umar Sharif},
      title = {Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five {SHA}-3 Finalists Using Xilinx and Altera {FPGAs}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2012/368},
      year = {2012},
      url = {https://eprint.iacr.org/2012/368}
}