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Paper 2011/670
SHA-3 on ARM11 processors
Peter Schwabe and Bo-Yin Yang and Shang-Yi Yang
Abstract
This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. We report new speed records for all of the six implemented functions. For example our implementation of the round-3 version of JH-256 is 35% faster than the fastest implementation of the round-2 version of JH-256 in eBASH. Scaled with the number of rounds this is more than a 45% improvement.We also improve upon previous assembly implementations for 32-bit ARM processors. For example the implementation of Groestl-256 described in this paper is about 20% faster than the arm32 implementation in eBASH.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- SHA-3ARM processorssoftware implementation
- Contact author(s)
- peter @ cryptojedi org
- History
- 2011-12-16: received
- Short URL
- https://ia.cr/2011/670
- License
-
CC BY