Paper 2011/557

An Improved Trace Driven Instruction Cache Timing Attack on RSA

Chen Cai-Sen, Wang Tao, Chen Xiao-Cen, and Zhou Ping

Abstract

The previous I-cache timing attacks on RSA which exploit the instruction path of a cipher were mostly proof-of-concept, and it is harder to put them into practice than D-cache timing attacks. We propose a new trace driven timing attack model based on spying on the whole I-cache. An improved analysis algorithm of the exponent using the characteristic of the size of the window is advanced, which could further reduce the search space of the bits of the key than the former and provide an error detection mechanism to detect some erroneous decisions of the operation sequence. We implemented an attack on RSA of OpenSSL under a practical environment, proving that the feasibility and effectiveness of I-Cache timing attack could be improved.

Metadata
Available format(s)
PDF
Category
Public-key cryptography
Publication info
Published elsewhere. Unknown where it was published
Keywords
Instruction cache-timing attacksside channel attackRSA cryptographic algorithmTrace-driven.
Contact author(s)
caisenchen @ 163 com
History
2011-10-11: received
Short URL
https://ia.cr/2011/557
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2011/557,
      author = {Chen Cai-Sen and Wang Tao and Chen  Xiao-Cen and Zhou Ping},
      title = {An Improved Trace Driven Instruction Cache Timing Attack on {RSA}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2011/557},
      year = {2011},
      url = {https://eprint.iacr.org/2011/557}
}
Note: In order to protect the privacy of readers, eprint.iacr.org does not use cookies or embedded third party content.