Cryptology ePrint Archive: Report 2011/258

A High Speed Pairing Coprocessor Using RNS and Lazy Reduction

Gavin Xiaoxu Yao and Junfeng Fan and Ray C.C. Cheung and Ingrid Verbauwhede

Abstract: In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for more than one multiplication, the computational complexity of pairings can be largely reduced. The design is prototyped on a Xilinx Virtex-6 FPGA, which utilizes 7023 slices and 32 DSPs, and finishes one 254-bit optimal ate pairing computation in 0.664 ms.

Category / Keywords: implementation / RNS, Moduli Selection, Hardware Implementation of Pairing, FPGA

Date: received 24 May 2011

Contact author: hehelaoyao at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20110528:032912 (All versions of this report)

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