Paper 2011/258

A High Speed Pairing Coprocessor Using RNS and Lazy Reduction

Gavin Xiaoxu Yao, Junfeng Fan, Ray C. C. Cheung, and Ingrid Verbauwhede

Abstract

In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for more than one multiplication, the computational complexity of pairings can be largely reduced. The design is prototyped on a Xilinx Virtex-6 FPGA, which utilizes 7023 slices and 32 DSPs, and finishes one 254-bit optimal ate pairing computation in 0.664 ms.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
RNSModuli SelectionHardware Implementation of PairingFPGA
Contact author(s)
hehelaoyao @ gmail com
History
2011-05-28: received
Short URL
https://ia.cr/2011/258
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2011/258,
      author = {Gavin Xiaoxu Yao and Junfeng Fan and Ray C. C.  Cheung and Ingrid Verbauwhede},
      title = {A High Speed Pairing Coprocessor Using RNS and Lazy Reduction},
      howpublished = {Cryptology ePrint Archive, Paper 2011/258},
      year = {2011},
      note = {\url{https://eprint.iacr.org/2011/258}},
      url = {https://eprint.iacr.org/2011/258}
}
Note: In order to protect the privacy of readers, eprint.iacr.org does not use cookies or embedded third party content.