Cryptology ePrint Archive: Report 2010/406

Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf

Julien Francq and CÚline Thuillet

Abstract: Recent cryptanalysis on SHA-1 family has led the NIST to call for a public competition named SHA-3 Contest. Efficient implementations on various platforms are a criterion for ranking performance of all the candidates in this competition. It appears that most of the hardware architectures proposed for SHA-3 candidates are basic. In this paper, we focus on an optimized implementation of the Shabal candidate. We improve the state-of-the-art using the unfolding method. This transformation leads to unroll a part of the Shabal core. More precisely, our design can produce a throughput over 3 Gbps on Virtex-5 FPGAs, with a reasonable area usage.

Category / Keywords: implementation / hash functions

Date: received 21 Jul 2010

Contact author: julien francq at eads com

Available format(s): PDF | BibTeX Citation

Version: 20100721:131533 (All versions of this report)

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