Cryptology ePrint Archive: Report 2010/371
Compact hardware for computing the Tate pairing over 128-bit-security supersingular curves
Abstract: This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such curves are usually restricted to lower levels of security because of their bounded embedding degree, aiming for the recommended security of 128 bits implies considering them over very large finite fields. We however manage to mitigate this effect by considering curves over field extensions of moderately-composite degree, hence taking advantage of a much easier tower field arithmetic. This technique of course lowers the security on the curves, which are then vulnerable to Weil descent attacks, but a careful analysis allows us to maintain their security above the 128-bit threshold.
As a proof of concept of the proposed method, we detail an FPGA accelerator for computing the Tate pairing on a supersingular curve over GF(3^(5*97)), which satisfies the 128-bit security target. On a mid-range Xilinx Virtex-4 FPGA, this accelerator computes the pairing in 2.2 ms while requiring no more than 4755 slices.
Category / Keywords: implementation / Tate pairing, supersingular elliptic curves, FPGA implementation.
Date: received 28 Jun 2010, last revised 13 Sep 2010
Contact author: Nicolas Estibals at loria fr
Available format(s): PDF | BibTeX Citation
Version: 20100913:153425 (All versions of this report)
Short URL: ia.cr/2010/371
Discussion forum: Show discussion | Start new discussion
[ Cryptology ePrint archive ]