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Paper 2010/364
A Compact FPGA Implementation of the SHA-3 Candidate ECHO
Jean-Luc Beuchat and Eiji Okamoto and Teppei Yamazaki
Abstract
We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining variable and the message block in the register file allows one to design a compact control unit based on a 4-bit counter, an 8-bit counter, and a simple Finite State Machine. A fully autonomous implementation of ECHO on a Xilinx Virtex-5 FPGA requires $127$ slices and a single memory block to store the internal state, and achieves a throughput of $72$Mbps.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Contact author(s)
- jeanluc beuchat @ gmail com
- History
- 2010-06-25: received
- Short URL
- https://ia.cr/2010/364
- License
-
CC BY