Cryptology ePrint Archive: Report 2010/292
A Low-Area yet Performant FPGA Implementation of Shabal
Jérémie Detrey and Pierrick Gaudry and Karim Khalfallah
Abstract: In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice.
According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.
Category / Keywords: implementation / SHA-3, Shabal, low area, FPGA implementation
Date: received 16 May 2010, last revised 29 Sep 2010
Contact author: Jeremie Detrey at loria fr
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Version: 20100929:143854 (All versions of this report)
Short URL: ia.cr/2010/292
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